
module riscv_clk(input RST, input CLK_50M, output clk);

    reg clk_r0;
    reg clk_r1;

    always @(posedge CLK_50M or negedge RST) begin
        if (!RST)
            clk_r0 <= 0;
        else
            clk_r0 <= ~clk_r0;
    end

    always @(posedge clk_r0 or negedge RST) begin
        if (!RST)
            clk_r1 <= 0;
        else
            clk_r1 <= ~clk_r1;
    end

    assign clk = clk_r1;

endmodule

